Debug cores for FPGAs,
independent of the vendor.

IPDBG provides small debug cores for your design and host tools that connect to them over JTAG, UART or your own transport, usually without extra pins. The same cores and tools work on AMD/Xilinx, Intel, Lattice, Efinix, Gowin and Microchip FPGAs.

Get started Source on GitHub

How it works

Each host tool talks to exactly one core in the FPGA over its own TCP port. With JTAG, OpenOCD carries all connections over one physical link, and a hub in the FPGA distributes them to the cores. Several tools can run at the same time.

Host tools connect over TCP to OpenOCD, which reaches the JTAG TAP and hub in the FPGA; the hub connects to the Logic Analyzer, Waveform Generator, BusAccess and IoProbe cores. Alternatively, one tool connects through a UART bridge and the UART transport to one core, without a hub.

Features

Four cores, each with its host-side counterpart.

Logic Analyzer

Capture internal signals with triggers and analyse them in sigrok / PulseView, with all sigrok protocol decoders and FSM states shown by name. Scriptable through the libsigrok C/C++ API and Python bindings.

Details →

Waveform Generator

Play waveforms into your design from sigrok or from a C library with C++, Python and Octave bindings. Repeated or one-shot, optionally double-buffered for glitch-free updates.

Documentation →

BusAccess

Bus master for AXI4-Lite, Wishbone, AHB, APB, Avalon and RISC-V DMI. Read and write registers from a C library or its C++, Python and Octave bindings, for scripted tests and bring-up.

Documentation →

IoView / IoProbe

Read and set individual signals interactively: IoProbe is the core in the FPGA, IoView the host application.

Documentation →
PulseView showing an SPI master FSM: the states decoded by name, the SPI transfers and the ADXL345 register accesses
An SPI master FSM reading an ADXL345: the enum decoder shows the FSM states by name, the SPI and ADXL345 decoders the transfers.
PulseView decoding an I2C read from an LM75 temperature sensor
An I²C frame generated in Octave, played by the Waveform Generator, captured by the Logic Analyzer and decoded as an LM75 temperature.
IoView window with input LEDs and output check boxes
IoView reading inputs and setting outputs of an IoProbe core.
All screenshots were taken with the co-simulation, no hardware needed. The scripts are in sw/CoSim/examples.

Supported devices

JTAG through the vendor's user scan chain, so no extra pins are needed.

AMD/XilinxSpartan-3, -6, -7, Virtex-4, -6, 7 Series, Zynq-7000, UltraScale*, UltraScale+*
Intel/AlteraArria II/II GZ/V/V GZ, Cyclone III/IV/IV E/V/10 LP, MAX V, MAX 10, Stratix III/V
LatticeECP2, ECP3, ECP5, Certus
EfinixTrion, Titanium
GowinGW1N
Microchip/ActelProASIC3

* Same BSCANE2 primitive as the 7 Series; less tested so far.

Generic JTAGSoft JTAG on 4 user I/Os, for any other FPGA.
UART2 user I/Os per core. SPI and I²C are planned.
Your ownE.g. a microcontroller running lwIP in front of a memory-mapped FPGA.

Get started

Try it without hardware: the co-simulation replaces the FPGA and the JTAG adapter with GHDL, and everything above it stays the same. 

# terminal 1
cd sw/CoSim && make && ./CoSim

# terminal 2
cd sw/CoSim && openocd -f ipdbg_JtagSim.cfg

# then connect
sigrok-cli --driver=ipdbg-la:conn=tcp-raw/127.0.0.1/4242 --scan

The demo design serves all four cores (ports 4242–4245) and loops the Waveform Generator back into the Logic Analyzer. CoSim documentation →